VLSI BASED PROJECTS

  1. LOW-POWER AND AREA-EFFICIENT CARRY SELECT ADDER   A  B  C  D
  2. DESIGN AND CHARACTERIZATION OF PARALLEL PREFIX ADDERS USING FPGAS   A  B  C  D
  3. SIMULATION OF IMAGE ENCRYPTION USING AES ALGORITHM   A  B  C  D
  4. AN AUTONOMOUS VECTOR/SCALAR FLOATING POINT COPROCESSOR FOR FPGAS   A  B  C  D
  5. A FPGA IEEE-754-2008 DECIMAL64 FLOATING-POINT ADDER/SUBTRACTOR   A  B  C  D
  6. IMPLEMENTATION OF CONVOLUTIONAL ENCODER AND VITERBI DECODER USING VERILOG HDL   A  B  C  D
  7. DESIGN AND SIMULATION OF UART SERIAL COMMUNICATION MODULE BASED ON VHDL   A  B  C  D
  8. DESIGN OF THREE-LIFT CONTROLLER BASED ON FPGA   A  B  C  D
  9. A REVIEW ON POWER OPTIMIZATION OF LINEAR FEED BACK SHIFT REGISTER (LFSR) FOR LOW POWER BIST   A  B  C  D
  10. THE DESIGN OF AN 8-BIT CISC CPU BASED ON FPGA   A  B  C  D
  11. OPTIMIZED DESIGN OF UART IP SOFT CORE BASED ON DMA MODE   A  B  C  D
  12. DESIGN OF SHA-1 ALGORITHM BASED ON FPGA   A  B  C  D
  13. IMPLEMENTATION OF NON-PIPELINED AND PIPELINED DATA ENCRYPTION STANDARD (DES) USING XILINX VIRTEX-6 FPGA TECHNOLOGY   A  B  C  D
  14. FPGA IMPLEMENTATION OF PIPELINED 2D-DCT AND QUANTIZATION ARCHITECTURE FOR JPEG IMAGE COMPRESSION   A  B  C  D
  15. A NEW VLSI ARCHITECTURE OF PARALLEL MULTIPLIER–ACCUMULATOR BASED ON RADIX-2 MODIFIED BOOTH ALGORITHM   A  B  C  D
  16. TEST DATA COMPRESSION USING EFFICIENT BIT MASK AND DICTIONARY SELECTION METHOD   A  B  C  D
  17. FPGA IMPLEMENTATION OF EFFICIENT FFT ALGORITHM BASED ON COMPLEX SEQUENCE   A  B  C  D
  18. SIMPLE TRAFFIC LIGHT CONTROLLER: A DIGITAL SYSTEM DESIGN PRODUCT   A  B  C  D
  19. IMPLEMENTATION OF FIR FILTER ON FPGA USING DAOBC ALGORITHM   A  B  C  D
  20. FPGA BASED IMPLEMENTATION OF HIGH PERFORMANCE ARCHITECTURAL LOW LEVEL POWER 32 BIT RISC CORE   A  B  C  D
  21. A FAST VLSI DESIGN OF SMS4 CIPHER BASED ON TWISTED BDD S-BOX ARCHITECTURE   A  B  C  D
  22. A FPGA IEEE-754 2008 DECIMAL 64 FLOATING POINT MULTIPLIER   A  B  C  D
  23. DESIGN AND IMPLEMENTATION OF LOSSLESS HIGH SPEED DATA COMPRESSION AND DECOMPRESSION USING VHDL   A  B  C  D
  24. DESIGN AND IMPLEMENTATION OF ENCRYPTION MODULE IN DES FOR SECURITY USING VERILOG   A  B  C  D
  25. DESIGN AND IMPLEMENTATION OF  DECRYPTION MODULE IN DES FOR SECURITY USING VERILOG   A  B  C  D
  26. IMPLEMENTATION OF REAL TIME CANDY MECHANIC USING VHDL   A  B  C  D
  27. DESIGN AND IMPLEMENTATION OF PATTERN GENERATOR FOR CIRCUIT UNDER TEST USING VERILOG   A  B  C  D
  28. EFFICIENT DESIGN OF BUTTERFLY ARCHITECTURE FOR RADIX 8  FAST FOURIER TRANSFORM USING VHDL   A  B  C  D
  29. DESIGN AND IMPLEMENTATION OF  DIGITAL CODE LOCK USING VHDL   A  B  C  D
  30. IMPLEMENTATION OF FIRST IN FIRST OUT DESIGN  USING VHDL   A  B  C  D
  31. VLSI DESIGN OF  TRAFFIC LIGHT CONTROLLER USING VHDL   A  B  C  D
  32. DESIGN AND IMPLEMENTATION OF  ENCRYPTION MODULE FOR AES CORE USING VERILOG   A  B  C  D
  33. DESIGN AND IMPLEMENTATION OF  DECRYPTION MODULE FOR AES CORE USING VERILOG   A  B  C  D
  34. DESIGN AND IMPLEMENTATION OF ELEVATOR CONTROLLER USING VHDL   A  B  C  D
  35. DESIGN AND IMPLEMENTATION OF  LFSR FOR LOW POWER APPLICATIONS USING VERILOG   A  B  C  D
  36. DESIGN AND IMPLEMENTATION OF  SERIALIZER AND DESERIALIZER  USING VHDL   A  B  C  D
  37. IMPLEMENTATION OF  FREQUENCY DISTRIBUTOR MODULE USING VHDL   A  B  C  D
  38. DESIGN AND IMPLEMENTATION OF  VENDING MACHINE CONTROLLER USING VHDL   A  B  C  D
  39. DESIGN AND IMPLEMENTATION OF  FINITE IMPULSE RESPONSE FILTER USING VHDL   A  B  C  D
  40. VLSI DESIGN OF 8 BIT MICROPROCESSOR IMPLEMENTATION USING VHDL   A  B  C  D
  41. DESIGN AND IMPLEMENTATION OF  ARRAY MULTIPLIER IN VERILOG   A  B  C  D
  42. DESIGN AND IMPLEMENTATION OF  STATE MACHINE CONTROLLER   A  B  C  D
  43. DESIGN AND IMPLEMENTATION OF  CONTENT ADDRESSABLE MEMORY USING VHDL   A  B  C  D
  44. DESIGN AND IMPLEMENTATION OF  HOUSE HOLD ALARM SYSTEM USING VHDL   A  B  C  D
  45. VLSI DESIGN OF  REDUCED INSTRUCTION SET COMPUTER PROCESSOR CORE USING VHDL   A  B  C  D
  46. VLSI IMPLEMENTATION OF  MEMORY CORE DESIGN USING VHDL   A  B  C  D
  47. DESIGN AND IMPLEMENTATION OF RANDOM NUMBER GENERATOR USING VERILOG   A  B  C  D
  48. DESIGN AND IMPLEMENTATION OF USB TRANSMITTER   A  B  C  D
  49. DESIGN AND IMPLEMENTATION OF BOOTH MULTIPLIER   A  B  C  D
  50. DESIGN AND IMPLEMENTATION OF WALLACE TREE MULTIPLIER   A  B  C  D
  51. PERFORMANCE EVALUATION OF HIGH SPEED AND LOW POWER ADDERS   A  B  C  D
  52. DESIGN OF AN ATM  (AUTOMATED TELLER MACHINE) CONTROLLER   A  B  C  D

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